industrial temperature range IDT74LVCH162374A 3.3v cmos 16-bit edge-triggered d-type flip-flop 1 january 2004 industrial temperature range the idt logo is a registered trademark of integrated device technology, inc. ? 2004 integrated device technology, inc. dsc-4678/2 features: ? typical t sk(o) (output skew) < 250ps ? esd > 2000v per mil-std-883, method 3015; > 200v using machine model (c = 200pf, r = 0) ?v cc = 3.3v 0.3v, normal range ?v cc = 2.7v to 3.6v, extended range ? cmos power levels (0.4 w typ. static) ? all inputs, outputs, and i/o are 5v tolerant ? available in ssop and tssop packages functional block diagram applications: ? 5v and 3.3v mixed voltage systems ? data communication and telecommunication systems drive features: ? balanced output drivers: 12ma ? low switching noise IDT74LVCH162374A description: the lvch162374a 16-bit edge-triggered d-type flip-flop is built using advanced dual metal cmos technology. this high-speed, low-power register is ideal for use as a buffer register for data synchronization and storage. the output enable ( oe ) and clock (clk) controls are organized to operate each device as two 8-bit registers or one 16-bit register with common clock. flow-through organization of signal pins simplifies layout. all inputs are designed with hysteresis for improved noise margin. all pins of the lvch162374a can be driven from either 3.3v or 5v devices. this feature allows the use of this device as a translator in a mixed 3.3v/5v supply system. the lvch162374a has series resistors in the device output structure which will significantly reduce line noise when used with light loads. this driver has been developed to drive 12ma at the designated thresholds. the lvch162374a has ?bus-hold? which retains the inputs? last state whenever the input goes to a high impedance. this prevents floating inputs and eliminates the need for pull-up/down resistors. 3.3v cmos 16-bit edge triggered d-type flip- flop with 3-state outputs, 5 volt tolerant i/o, bus-hold 1 oe 1d c1 1 clk 1 d 1 1 q 1 to seven other channels 2 oe 1d c1 2 clk 2 d 1 2 q 1 1 48 47 2 24 25 36 13 to seven other channels
industrial temperature range 2 IDT74LVCH162374A 3.3v cmos 16-bit edge-triggered d-type flip-flop ssop/ tssop top view pin configuration symbol description max unit v term terminal voltage with respect to gnd ?0.5 to +6.5 v t stg storage temperature ?65 to +150 c i out dc output current ?50 to +50 ma i ik continuous clamp current, ?50 ma i ok v i < 0 or v o < 0 i cc continuous current through each 100 ma i ss v cc or gnd absolute maximum ratings (1) note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. note: 1. as applicable to the device type. symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 4.5 6 pf c out output capacitance v out = 0v 6.5 8 pf c i/o i/o port capacitance v in = 0v 6.5 8 pf capacitance (t a = +25c, f = 1.0mhz) notes: 1. h = high voltage level x = don?t care l = low voltage level z = high-impedance 2. output level before the indicated steady-state input conditions were established. inputs outputs x oe xclk xdx xqx l hh l ll l h or l x q (2) hxx z function table (each flip-flop) (1) pin names description x d x data inputs (1) xclk clock inputs x q x 3-state outputs x oe 3-state output enable inputs (active low) pin description note: 1. these pins have "bus-hold". all other pins are standard inputs, outputs, or i/os. 1 q 2 gnd v cc gnd gnd 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 40 41 42 43 44 45 46 47 48 1 1 q 1 1 oe 1 q 4 1 q 3 1 q 6 1 q 5 1 q 8 1 q 7 2 q 1 2 q 3 2 q 2 2 q 4 v cc 2 q 5 2 q 6 gnd 2 q 7 2 q 8 2 oe 1 d 2 gnd v cc gnd gnd 1 d 1 1 clk 1 d 4 1 d 3 1 d 6 1 d 5 1 d 8 1 d 7 2 d 1 2 d 3 2 d 2 2 d 4 v cc 2 d 5 2 d 6 gnd 2 d 7 2 d 8 2 clk
industrial temperature range IDT74LVCH162374A 3.3v cmos 16-bit edge-triggered d-type flip-flop 3 symbol parameter test conditions min. typ. (1) max. unit v ih input high voltage level v cc = 2.3v to 2.7v 1.7 ? ? v v cc = 2.7v to 3.6v 2 ? ? v il input low voltage level v cc = 2.3v to 2.7v ? ? 0.7 v v cc = 2.7v to 3.6v ? ? 0.8 i ih input leakage current v cc = 3.6v v i = 0 to 5.5v ? ? 5a i il i ozh high impedance output current v cc = 3.6v v o = 0 to 5.5v ? ? 10 a i ozl (3-state output pins) i off input/output power off leakage v cc = 0v, v in or v o 5.5v ? ? 50 a v ik clamp diode voltage v cc = 2.3v, i in = ?18ma ? ?0.7 ?1.2 v v h input hysteresis v cc = 3.3v ? 100 ? mv i ccl quiescent power supply current v cc = 3.6v v in = gnd or v cc ?? 10a i cch i ccz 3.6 v in 5.5v (2) ?? 10 ? i cc quiescent power supply current one input at v cc - 0.6v, other inputs at v cc or gnd ? ? 500 a variation dc electrical characteristics over operating range following conditions apply unless otherwise specified: operating condition: t a = ?40c to +85c notes: 1. typical values are at v cc = 3.3v, +25c ambient. 2. this applies in the disabled state only. bus-hold characteristics symbol parameter (1) test conditions min. typ. (2) max. unit i bhh bus-hold input sustain current v cc = 3v v i = 2v ? 75 ? ? a i bhl v i = 0.8v 75 ? ? i bhh bus-hold input sustain current v cc = 2.3v v i = 1.7v ? ? ? a i bhl v i = 0.7v ? ? ? i bhho bus-hold input overdrive current v cc = 3.6v v i = 0 to 3.6v ? ? 500 a i bhlo notes: 1. pins with bus-hold are identified in the pin description. 2. typical values are at v cc = 3.3v, +25c ambient.
industrial temperature range 4 IDT74LVCH162374A 3.3v cmos 16-bit edge-triggered d-type flip-flop switching characteristics (1) v cc = 2.7v v cc = 3.3v 0.3v symbol parameter min. max. min. max. unit t plh propagation delay 2 6.5 2 6.2 ns t phl xclk to xqx t pzh output enable time 1.5 6.3 1.5 6.1 ns t pzl x oe to xqx t phz output disable time 1.5 6.2 1.5 6 ns t plz x oe to xqx t su set-up time high or low, xdx before xclk 2.5 ? 2.5 ? ns t h hold time high or low, xdx after xclk 1.5 ? 1.5 ? ns t w xclk pulse width high or low 3 ? 3 ? ns t sk (o) output skew (2) ?? ? 500 ps notes: 1. see test circuits and waveforms. t a = ? 40c to + 85c. 2. skew between any two outputs of the same package and switching in the same direction. note: 1. v ih and v il must be within the min. or max. range shown in the dc electrical characteristics over operating range table for the appropriat e v cc range. t a = ? 40c to + 85c. output drive characteristics symbol parameter test conditions (1) min. max. unit v oh output high voltage v cc = 2.3v to 3.6v i oh = ? 0.1ma v cc ? 0.2 ? v v cc = 2.3v i oh = ? 4ma 1.9 ? i oh = ? 6ma 1.7 ? v cc = 2.7v i oh = ? 4ma 2.2 ? i oh = ? 8ma 2 ? v cc = 3v i oh = ? 6ma 2.4 ? i oh = ? 12ma 2 ? v ol output low voltage v cc = 2.3v to 3.6v i ol = 0.1ma ? 0.2 v v cc = 2.3v i ol = 4ma ? 0.4 i ol = 6ma ? 0.55 v cc = 2.7v i ol = 4ma ? 0.4 i ol = 8ma ? 0.6 v cc = 3v i ol = 6ma ? 0.55 i ol = 12ma ? 0.8 operating characteristics, v cc = 3.3v 0.3v, t a = 25c symbol parameter test conditions typical unit c pd power dissipation capacitance per flip-flop outputs enabled c l = 0pf, f = 10mhz ? pf c pd power dissipation capacitance per flip-flop outputs disabled ?
industrial temperature range IDT74LVCH162374A 3.3v cmos 16-bit edge-triggered d-type flip-flop 5 open v load gnd v cc pulse generator d.u.t. 500 ? 500 ? c l r t v in v out (1, 2) lvc link input v ih 0v v oh v ol t plh1 t sk (x) output 1 output 2 t phl1 t sk (x) t plh2 t phl2 v t v t v oh v t v ol t sk (x) = t plh2 - t plh1 or t phl2 - t phl1 lvc link same phase input transition opposite phase input transition 0v 0v v oh v ol t plh t phl t phl t plh output v ih v t v t v ih v t lvc link data input 0v 0v 0v 0v t rem timing input asynchronous control synchronous control t su t h t su t h v ih v t v ih v t v ih v t v ih v t lvc link low-high-low pulse high-low-high pulse v t t w v t lvc link control input t plz 0v output normally low t pzh 0v switch closed output normally high enable disable switch open t phz 0v v lz v oh v t v t t pzl v load/2 v load/2 v ih v t v ol v hz lvc link test circuits and waveforms propagation delay test circuit for all outputs enable and disable times set-up, hold, and release times notes: 1. for t sk (o) output1 and output2 are any two outputs. 2. for t sk (b) output1 and output2 are in the same bank. definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. notes: 1. pulse generator for all pulses: rate 10mhz; t f 2.5ns; t r 2.5ns. 2. pulse generator for all pulses: rate 10mhz; t f 2ns; t r 2ns. output skew - t sk ( x ) pulse width note: 1. diagram shown for input control enable-low and input control disable-high. symbol v cc (1) = 3.3v0.3v v cc (1) = 2.7v v cc (2) = 2.5v0.2v unit v load 6 6 2 x vcc v v ih 2.7 2.7 vcc v v t 1.5 1.5 vcc / 2 v v lz 300 300 150 mv v hz 300 300 150 mv c l 50 50 30 pf test conditions switch position test switch open drain disable low v load enable low disable high gnd enable high all other tests open
industrial temperature range 6 IDT74LVCH162374A 3.3v cmos 16-bit edge-triggered d-type flip-flop ordering information corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com idt xx lvc xxxx xx package device type temp. range pv pa 162 74 shrink small outline package thin shrink small outline package 16-bit edge triggered d-type flip-flop -40c to +85c xxx family bus-hold 374a bus-hold double-density with resistors, 12ma h
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